UPD70F3114 Datasheet, PDF (268/692 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/COUNTER FUNCTION
Figure 9-30. Operation Timing in PWM Mode 2 (Sawtooth Wave) (1/2)
(a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2)
CM0n3 (d)
TM0n
count value
0000H
BFCMnx ^a
a
CM0nx
match
b
CM0n3 (e)
b
CM0nx
match
c
CM0nx
a
b
c
BFCMn3 d
e
f
CM0n3
Interrupt request
F/F
DTMnx
d
INTCM01x
e
f
INTCM0n3 INTCM01x INTCM0n3
Set by rising edge of
TM0CEn bit
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
t
t
t
t
t
Remarks 1. The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register
are 1, and transfer from BFCMn3 to CM0n3, or from BFCMnx to CM0nx is enabled. Transfer is
not performed when BFTE3 = 0 or BFTEN = 0.
2. n = 0, 1
3. x = 0 to 2
4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock)
5. The above figure shows an active-high case.
6. INTCM01x is generated on a match between TM01 and CM01x (a and b in the above figure).
INTCM00x is not generated.
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User’s Manual U15195EJ5V0UD