UPD70F3114 Datasheet, PDF (449/692 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 10 SERIAL INTERFACE FUNCTION
(c) Cautions
<1> Operation upon occurrence of overrun error during 2-frame continuous reception
• During normal operation
Reception completion interrupt (INTSR1) generated at end of reception of 2nd frame, no error
RXD1
Frame 1
Frame 2
• Reception of 3rd frame started before performing reception processing
Reception completion interrupt (INTSR1) generated at end of reception of 2nd frame, no error
RXD1
Frame 1
Frame 2
Reception interrupt not generated at end of reception of 3rd frame, occurrence of error
RXD1
Frame 3
Frame 3
Value of OVE1 bit of ASIS1 register becomes 1.
• Start of reception of 3rd frame and 4th frame before performing reception processing
Reception completion interrupt (INTSR1) generated at end of reception of 2nd frame, no error
RXD1
Frame 1
Frame 2
No reception completion interrupt generated at end of reception of 3rd frame, occurrence of error
RXD1
Frame 3
Frame 3
Value of OVE1 bit of ASIS1 register becomes 1.
Reception completion interrupt (INTSR1) generated at end of reception of 4th frame, no error
RXD1
Frame 3
Frame 4
Value of OVE1 frame of ASIS1 register remains 1.
• Start of reception of 3rd frame before performing reception processing, start of reception of
4th frame after reception processing
Reception completion interrupt (INTSR1) generated at end of reception of 2nd frame, no error
RXD1
Frame 1
Frame 2
Reception completion interrupt not generated at end of reception of 3rd frame, occurrence of error
RXD1
Frame 3
Frame 3
Value of OVE1 bit of ASIS1 register becomes 1.
Value of OVE1 flag becomes 0 during reception processing.
Reception completion interrupt (INTSR1) generated at end of reception of 4th frame, no error
RXD1
Frame 3
No occurrence of error
Frame 4
User’s Manual U15195EJ5V0UD
449