UPD70F3114 Datasheet, PDF (237/692 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/COUNTER FUNCTION
Next, an example of the operation timing, which depends on the values set to CM0n0 to CM0n2, CM0n4, and
CM0n5 (BFCMn0 to BFCMn2, BFCMn4, BFCMn5) is shown.
(a) When CM0nx (BFCMnx) ≥ CM0n3 is set
Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx ≥ CM0n3) (1/2)
(a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2)
TM0n
count value
0000H
BFCMnx a
CM0n3
a
a
CM0nx
match
CM0nx
match
BFCMnx ≥ CM0n3
CM0n3
CM0nx match
(BFCMnx = CM0n3)
BFCMnx ≥ CM0n3
CM0nx
Interrupt request
F/F
a
BFCMnx ≥ CM0n3
INTCM0n3
INTTM0n
INTCM0n3
INTTM0n
INTCM01x INTCM01x
INTCM01x
(BFCM1x = CM013)
DTMnx
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
t
t
Remarks 1. n = 0, 1
2. x = 0 to 2
3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock)
4. The above figure shows an active-high case.
5. INTCM01x is generated on a match between TM01 and CM01x (a in the above figure).
INTCM00x is not generated.
User’s Manual U15195EJ5V0UD
237