UPD70F3114 Datasheet, PDF (260/692 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/COUNTER FUNCTION
Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2) (2/2)
(b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5)
TM0n
count value
0000H
BFCMnx a
CM0n3
a
CM0nx
match
0000H
CM0nx
match
0000H
CM0n3
0000H
CM0nx
match
0000H
CM0nx
Interrupt request
a
0000H
0000H
0000H
0000H
INTCM0n3
INTCM0nx
INTTM0n
INTCM0nx
INTCM0n3
INTTM0n
INTCM0nx
Remarks 1. n = 0, 1
2. x = 4, 5
3. INTCM0nx is generated on a match between TM0n and CM0nx (a in the above figure).
Since TM0n = CM0n0 to CM0n2 = 0000H match is detected during up counting by TM0n, the F/F is just
set and is not reset. Therefore, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a high
level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a low level.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
Figure 9-28 shows the change timing from the 100% duty state.
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User’s Manual U15195EJ5V0UD