UPD70F3212 Datasheet, PDF (645/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 22 STANDBY FUNCTION
Table 22-10. Operation Status in Sub-IDLE Mode
Setting of Sub-IDLE
Operation Status
Item
Mode
When Main Clock Is Oscillating
When Main Clock Is Stopped
CPU
Stops operation
ROM correction
Stops operation
Subclock oscillator
Oscillation enabled
Interrupt controller
Timer P (TMP0)^{Note 1}
Stops operation
Stops operation
16-bit timers (TM00 to TM03)
TM00, TM02, TM03: Stop operation
TM01: Operable when INTWT is selected
as count clock
TM00, TM02, TM03: Stop operation
TM01: Operable when INTWT is selected
as count clock and fXT is selected as count
clock of WT
8-bit timers (TM50, TM51)
• Operable when TI5n is selected as count
clock
• Operable when INTTM010 is selected as
count clock and INTWT is selected as
count clock of TM01
• Operable when TI5n is selected as count
clock
• Operable when INTTM010 is selected as
count clock and when TM01 is enabled
in sub-IDLE mode
Timer H (TMH0)
Stops operation
Timer H (TMH1)
Operable when fXT is selected as count clock
Watch timer
Stops operation
Operable when fXT is selected as count clock
Watchdog timer 1
Operable
Stops operation
Watchdog timer 2
Operable when fXT is selected as count clock
Serial interface CSI00, CSI01
Stops operation
Operable when SCK0n input clock is
selected as operation clock
CSIA0, CSIA1
I²C0^{Note 2}
Stops operation
Stops operation
UART0
Operable when ASCK0 is selected as count clock
UART1
Stops operation
Key interrupt function
Operable
A/D converter
D/A converter
Stops operation
ch0: Stops operation (retains output)^{Note 3}
ch1: (For other than the following conditions, refer to Note 3.)
Operable when real-time output mode is selected and fXT is selected as count clock of
TMH1.
Real-time output
Operable when INTTM5n is selected as real-time output trigger and TI5n is selected as
count clock of TM5n
Port function
Retains status before sub-IDLE mode was set.
External bus interface
Refer to 2.2 Pin Status.
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of the
internal RAM are retained as they were before the sub-IDLE mode was set.
Notes 1.
2.
3.
Only in the µPD703215, 703215Y, 70F3215H, 70F3215HY
Only in the µPD703212Y, 703213Y, 703214Y, 703215Y, 70F3214Y, 70F3214HY, 70F3215HY
If the sub-IDLE mode is set immediately after D/A conversion has started (during conversion), the D/A
converter continues operating until D/A conversion is complete and retains the output at the end of D/A
conversion.
Remark n = 0, 1
User’s Manual U16890EJ1V0UD
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