UPD70F3212 Datasheet, PDF (426/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 14 A/D CONVERTER
(7) Interrupt request flag (ADIC.ADIF bit)
Even when the ADS register is changed, the ADIF bit is not cleared (0).
Therefore, if the analog input pin is changed during A/D conversion, the ADIF bit may be set (1) because A/D
conversion of the previous analog input pin ends immediately before the ADS register is rewritten. In a such
case, note that if the ADIF bit is read immediately after the ADS register has been rewritten, the ADIF bit is set
(1) even though A/D conversion of the analog input pin after the change has not been completed.
When stopping A/D conversion once and resuming it, clear the ADIF bit (0) before resuming A/D conversion.
Figure 14-7. A/D Conversion End Interrupt Request Occurrence Timing
ADS rewrite
(ANIn conversion start)
ADS rewrite
(ANIm conversion start)
ANIm conversion is not complete
even though ADIF is set.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remark n = 0 to 7
m = 0 to 7
(8) Conversion results immediately after A/D conversion start
If the ADM.ADCS bit is set to 1 within 17 µs (14 µs when AVREF0 ≥ 4.0 V) after the ADM.ADCS2 bit has been
set to 1, or if the ADCS bit is set to 1 with the ADCS2 bit cleared to 0, the converted value immediately after
the A/D conversion operation has started may not satisfy the rating. Take appropriate measures such as
polling the A/D conversion end interrupt request signal (INTAD) and discarding the first conversion result.
(9) Reading A/D conversion result register (ADCR)
When the ADM or ADS register has been written, the contents of the ADCR register may become undefined.
When the conversion operation is complete, read the conversion results before writing to the ADM or ADS
register. A correct conversion result may not be able to be read at a timing other than the above.
When the CPU is operating on the subclock and main clock oscillation (fX) is stopped, do not read the ADCR
register.
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User’s Manual U16890EJ1V0UD