UPD70F3212 Datasheet, PDF (384/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 11 INTERVAL TIMER, WATCH TIMER
11.1.3 Registers
Interval timer BRG includes the following registers.
(1) Interval timer BRG mode register (PRSM)
PRSM controls the operation of interval timer BRG, selection of count clock, and clock supply to the watch
timer.
This register can be read or written in 8-bit or 1-bit units.
After reset, PRSM is cleared to 00H.
After reset: 00H R/W Address: FFFFF8B0H
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PRSM
0
0
0
BGCE
0
TODIS BGCS1 BGCS0
BGCE
0
1
Control of interval timer operation
Operation stopped, 8-bit counter cleared to 01H
Operate
TODIS
0
1
Control of clock supply for watch timer
Clock for watch timer not supplied
Clock for watch timer supplied
BGCS1 BGCS0
0
0
fX
0
1
fX/2
1
0
fX/4
1
1
fX/8
Selection of input clock (fBGCS)^Note
10 MHz
5 MHz
100 ns
200 ns
200 ns
400 ns
400 ns
800 ns
800 ns
1.6 µ s
4 MHz
250 ns
500 ns
1 µs
2 µs
Note Set these bits so that the following conditions are satisfied.
VDD = 4.0 to 5.5 V: fBGCS ≤ 10 MHz
VDD = 2.7 to 4.0 V: fBGCS ≤ 5 MHz
Cautions 1. Do not change the values of the TODIS, BGCS1, and
BGCS0 bits while interval timer BRG is operating (BGCE
bit = 1). Set the TODIS, BGCS1, and BGCS0 bits before
setting (1) the BGCE bit.
2. When the BGCE bit is cleared (to 0), the 8-bit counter is
cleared.
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User’s Manual U16890EJ1V0UD