UPD70F3212 Datasheet, PDF (378/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 10 8-BIT TIMER H
Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the
count clock frequency as fCNT, the carrier clock output cycle and duty are as follows.
Carrier clock output cycle = (N + M + 2)/fCNT
Duty = High level width: Carrier clock output width = (M + 1) : (N + M + 2)
Caution Be sure to set the CMPn1 register when starting the timer count operation (TMHEn bit = 1)
after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if
setting the same value to the CMPn1 register).
(4) Timing chart
The carrier output control timing is as follows.
Cautions 1. Set the values of the CMPn0 and CMPn1 registers in the range of 01H to FFH.
2. In the carrier generator mode, three operating clocks (signal selected by the
TMHMDn.CKSHn0 to TMHMDn.CKSHn2 bits) are required for actual transfer of the new
value to the register after the CMPn1 register has been rewritten.
3. Be sure to perform the TMCYCn.RMCn bit setting before the start of the count operation.
4. When using the carrier generator mode, set the 8-bit timer Hn count clock frequency to
six times the 8-bit timer/event counter 5n count clock frequency or higher.
378
User’s Manual U16890EJ1V0UD