UPD70F3212 Datasheet, PDF (600/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 20-4. Maskable Interrupt Servicing
INT input
INTC acknowledged
CPU processing
Interrupt mask
No
released?
Yes
Priority higher than
No
that of interrupt currently
being serviced?
Yes
Priority higher than
No
that of other interrupt
requests?
Yes
Highest default
No
priority of interrupt requests with
the same priority?
Yes
Maskable interrupt request
1
PSW. NP
0
1
PSW. ID
0
EIPC
EIPSW
ECR. EICC
PSW. EP
PSW. ID
ISPR.
corresponding-
bit^Note
PC
Restored PC
PSW
Exception code
0
1
1
Handler address
Interrupt servicing
Interrupt request pending
Interrupt request pending
Note For the ISPR register, refer to 20.3.6 In-service priority register (ISPR).
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User’s Manual U16890EJ1V0UD