UPD70F3212 Datasheet, PDF (619/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
20.6 Exception Trap
The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850ES/KG1, an illegal opcode trap (ILGOP: illegal opcode trap) is considered as an exception trap.
20.6.1 Illegal opcode
An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26
to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap is
generated.
15
11 10
54
0 31
27 26
23 22
16
0111
XXXXX1 1 1 1 1 1XXXXXXXXXX
XXXXXX 0
1 111
X: don’t care
Caution It is recommended not to use illegal opcode because instructions may newly be assigned in the
future.
(1) Operation
Upon generation of an exception trap, the CPU performs the following processing and transfers control to a
handler routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits.
<4> Loads the handler address (00000060H) for the exception trap routine to the PC and transfers control.
Figure 20-10 shows the exception trap processing flow.
User’s Manual U16890EJ1V0UD
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