UPD70F3212 Datasheet, PDF (569/861 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 19 I²C BUS
19.7 Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control
The setting of the IICC0.WTIM0 bit determines the timing by which the INTIIC0 signal is generated and the
corresponding wait control, as shown below.
Table 19-3. INTIIC0 Signal Generation Timing and Wait Control
WTIM0 Bit
During Slave Device Operation
During Master Device Operation
Address
Data Reception Data Transmission
Address
Data Reception Data Transmission
0
9^{Notes 1, 2}
8^{Note 2}
8^{Note 2}
9
8
8
1
9^{Notes 1, 2}
9^{Note 2}
9^{Note 2}
9
9
9
Notes 1.
2.
The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the SVA0 register.
At this point, an ACK signal is output regardless of the value set to the IICC0.ACKE0 bit. For a slave
device that has received an extension code, the INTIIC0 signal occurs at the falling edge of the eighth
clock.
When the address does not match after restart, the INTIIC0 signal is generated at the falling edge of the
ninth clock, but no wait occurs.
If the received address does not match the contents of the SVA0 register and extension codes have not
been received, neither the INTIIC0 signal nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
• Slave device operation: Interrupt and wait timing are determined depending on the conditions in Notes 1
and 2 above regardless of the WTIM0 bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• By setting the IICC0.WREL0 bit to 1
• By writing to the IIC0 register
• By start condition setting (IICC0.STT0 bit = 1)^Note
• By stop condition setting (IICC0.SPT0 bit = 1)^Note
Note Master only
When an 8-clock wait has been selected (WTIM0 bit = 0), the output level of the ACK signal must be
determined prior to wait cancellation.
User’s Manual U16890EJ1V0UD
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