MC68HC12D60 Datasheet, PDF (350/432 Pages) Motorola, Inc – Advance Information - Rev 4.0

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SDV — Shifter Data Valid
Shows that valid data is in the serial interface shift register. Used by
the BDM firmware.
0 = No valid data. Shift operation is not complete.
1 = Valid Data. Shift operation is complete.
TRACE — Asserted by the TRACE1 command
CLKSW — Clock Switch
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM communications.
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
19.4.9 INSTRUCTION - Hardware Instruction Decode
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
The hardware clears the INSTRUCTION register if 512 BCLK cycles
occur between falling edges from the host.
BIT 7
6
5
4
3
2
1
BIT 0
H/F
DATA
R/W
BKGND
W/B
BD/U
0
0
RESET:
0
0
0
0
0
0
0
0
INSTRUCTION — BDM Instruction Register (hardware command explanation)
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68HC(9)12D60 — Rev 4.0
MOTOROLA