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MC68HC12D60 Datasheet, PDF (183/432 Pages) Motorola, Inc – Advance Information - Rev 4.0 | |||
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Freescale Semiconductor, Inc.
Pulse Width Modulator
Introduction
CLOCK SOURCE
(ECLK or Scaled ECLK)
GATE
(CLOCK EDGE SYNC)
PWENx
SYNC
PWCNTx
CENTR = 1
RESET
(DUTY CYCLE)
8-BIT COMPARE =
PWDTYx
(PERIOD)
8-BIT COMPARE =
PWPERx
FROM PORT P
DATA REGISTER
T
Q
MUX
Q
PPOLx
MUX
TO PIN
DRIVER
PPOL = 1
PPOL = 0
PWDTY
(PWPER â PWDTY) Ã 2
PWPER Ã 2
PWDTY
Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel
68HC(9)12D60 â Rev 4.0
MOTOROLA
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com
Advance Information
183
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