MC68HC12D60 Datasheet, PDF (24/432 Pages) Motorola, Inc – Advance Information - Rev 4.0

Freescale Semiconductor, Inc.
General Description
1.3 Features
• 16-bit CPU12
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to
M68HC11
– 20-bit ALU
– Instruction queue
– Enhanced indexed addressing
• Multiplexed bus
– Single chip or expanded
– 16 address/16 data wide or 16 address/8 data narrow mode
• Two 8-bit ports with key wake-up interrupt (2 pins only are
available on 80QFP) and one I²C start bit detector (112TQFP
only)
• Memory
– 60K byte flash EEPROM, made of a 28K module and a 32K
module with 8K bytes protected BOOT section in each module
(68HC912D60)
– 60K byte ROM (68HC12D60)
– 1K byte EEPROM
– 2K byte RAM
• Analog-to-digital converters
– 2 x 8-channels, 10-bit resolution in 112TQFP
– 1 x 8-channels, 8-bit resolution in 80QFP
• 1M bit per second, CAN 2.0 A, B software compatible module
– Two receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
Advance Information
24
General Description
For More Information On This Product,
Go to: www.freescale.com
68HC(9)12D60 — Rev 4.0
MOTOROLA