MC68HC12D60 Datasheet, PDF (171/432 Pages) Motorola, Inc – Advance Information - Rev 4.0

Freescale Semiconductor, Inc.
Clock Functions
Clock Divider Chains
MCLK
TEN
REGISTER: TMSK2
BITS: PR2, PR1, PR0
0:0:0
÷ 2 ^0:0:1
MCEN
÷4
REGISTER: MCCTL
BITS: MCPR1, MCPR0
0:0
0:1
MODULUS
DOWN
COUNTER
÷ 2 ^0:1:0
÷ 2 ^0:1:1
÷ 2 ^1:0:0
÷ 2 ^1:0:1
÷ 2 ^1:1:0
÷ 2 ^1:1:1
PORT T7
PAEN
Prescaled MCLK
÷2
1:0
÷2
1:1
REGISTER: PACTL
BITS: PAEN, CLK1, CLK0
0:x:x
1:0:0
1:0:1
GATE
LOGIC _PAMOD
PULSE ACC
LOW BYTE
1:1:0
PACLK/256
1:1:1
PACLK/65536
(PAOV)
PACLK
PULSE ACC
HIGH BYTE
TO TIMER
MAIN
COUNTER
(TCNT)
Figure 12-8. Clock Chain for ECT
68HC(9)12D60 — Rev 4.0
MOTOROLA
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
Advance Information
171