MC68HC12D60 Datasheet, PDF (341/432 Pages) Motorola, Inc – Advance Information - Rev 4.0

Freescale Semiconductor, Inc.
Development Support
Background Debug Mode
during host-to-target transmissions to speed up rising edges. Since the
target does not drive the BKGD pin during this period, there is no need
to treat the line as an open-drain signal during host-to-target
transmissions.
B CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
OF BIT TIME
SYNCHRONIZATION
UNCERTAINTY
TARGET SENSES BIT
10 CYCLES
Figure 19-1. BDM Host to Target Serial Bit Timing
EARLIEST
START OF
NEXT BIT
B CLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED
START OF BIT
TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
EARLIEST
START OF
NEXT BIT
Figure 19-2. BDM Target to Host Serial Bit Timing (Logic 1)
68HC(9)12D60 — Rev 4.0
MOTOROLA
Development Support
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Advance Information
341