M2S050TS-1FGG144YI Datasheet, PDF (97/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

ADVANCE INFORMATION (Subject to Change)
SmartFusion2 System-on-Chip FPGAs
Table 2-81 • uSRAM (RAM64x18) in 64x18 Mode (continued)
Parameter
Description
trstrec
Read Asynchronous Reset Recovery Time (Pipelined Clock)
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
tr2q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
Read Asynchronous Reset to Output Propagation Delay
(With Pipe-Line Register Disabled)
tsrstsu
Read Synchronous Reset Setup Time
tsrsthd
Read Synchronous Reset Hold Time
tccy
Write Clock Period
tcclkmpwh Write Clock Minimum Pulse Width High
tcclkmpwl Write Clock Minimum Pulse Width Low
tblkcsu Write Block Setup Time
tblkchd Write Block Hold Time
tdincsu Write Input Data setup Time
tdinchd Write Input Data hold Time
taddrcsu Write Address Setup Time
taddrchd Write Address Hold Time
twecsu Write Enable Setup Time
twechd Write Enable Hold Time
–1
Min. Max.
0.546 –
0.085 –
– 0.938
– 1.588
0.189 –
0.074 –
1.012 –
0.506 –
0.297 –
0.332 –
TBD
–
TBD
–
0.002 –
TBD
–
TBD
–
0.32
–
TBD
–
Std.
Min. Max. Units
0.642 – ns
0.099 – ns
- 1.103 ns
- 1.868 ns
0.222
0.087
1.192
0.596
0.349
0.39
TBD
TBD
0.003
TBD
TBD
0.377
TBD
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
Revision 0
2- 79