M2S050TS-1FGG144YI Datasheet, PDF (83/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

ADVANCE INFORMATION (Subject to Change)
SmartFusion2 System-on-Chip FPGAs
I/O Register Specifications
Input Register
Table 2-73 • Input Data Enable Register Propagation Delays
Worst Commercial-Case Conditions: T_J = 85°C, VDD = 1.14 V
Parameter
Description
Measuring
Nodes
(from, to)* –1 Std. Units
tICLKQ Clock-to-Q of the Input Data Register
TBD TBD ns
tISUD Data Setup Time for the Input Data Register
TBD TBD ns
tIHD Data Hold Time for the Input Data Register
TBD TBD ns
tISUE Enable Setup Time for the Input Data Register
TBD TBD ns
tIHE Enable Hold Time for the Input Data Register
TBD TBD ns
tICLR2Q Asynchronous Clear-to-Q of the Input Data Register
TBD TBD ns
tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register
TBD TBD ns
tIREMCLR Asynchronous Clear Removal Time for the Input Data Register
TBD TBD ns
tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register
TBD TBD ns
tIREMPRE Asynchronous Preset Removal Time for the Input Data Register
TBD TBD ns
tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register
TBD TBD ns
tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data
Register
TBD TBD ns
tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data
Register
TBD TBD ns
tICKMPWH Clock Minimum Pulse Width High for the Input Data Register
TBD TBD ns
tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register
TBD TBD ns
*For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-11 on page 2-14
for derating values.
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