M2S050TS-1FGG144YI Datasheet, PDF (4/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

SmartFusion2 System-on-Chip FPGAs
Table 1 • SmartFusion2 SoC FPGA Product Family
Features
Logic Modules (4-Input LUT)
LSRAM 18K Blocks
uSRAM 1K Blocks
Total RAM (Bits)
Math Blocks
PLLs and CCCs
Cortex-M3 Processor + Instruction Cache
eNVM (Bytes)
eSRAM (Bytes)
eSRAM (Bytes non-SECDED)
CAN 2.0 A and B
Triple speed Ethernet 10/100/1000
USB 2.0 High Speed On-The-Go
Multi-Mode UART
SPI
I2C
Timer
DDR Controllers
SERDES Channels
PCIe Endpoint × 4
3.3 V Multi-Standard User I/Os (MSIOs)
MSIOD I/Os
DDRIO I/Os
Total User I/Os
SERDES I/Os
Total User I/Os + SERDES I/Os
M2S005
4,956
10
11
191K
11
2
Yes
128K
64K
80K
1
1
1
2
2
2
2
1x18
0
0
123
28
66
217
0
217
M2S010
9,744
21
22
400K
22
2
Yes
256K
64K
80K
1
1
1
2
2
2
2
1x18
4
1
123
40
70
233
16
249
M2S025
23,988
31
34
592K
34
4
Yes
256K
64K
80K
1
1
1
2
2
2
2
1x18
4
1
159
40
90
289
16
305
M2S050
48,672
69
72
1,314K
72
6
Yes
256K
64K
80K
1
1
1
2
2
2
2
2x36
8
2
139
62
176
377
32
409
M2S080
82,232
160
160
3,040K
160
8
Yes
512K
64K
80K
1
1
1
2
2
2
2
2x36
8
2
292
106
176
574
64
638
M2S120
120,348
236
240
4,500K
240
8
Yes
512K
64K
80K
1
1
1
2
2
2
2
2x36
16
4
292
106
176
574
64
638
I/Os Per Package
Table 2 • I/Os per Package and Package Options
Package Options
VF400
Pin Count
400
Ball Pitch (mm)
0.8
Length × Width (mm\mm)
17 × 17
I/Os XCVRs
M2S005
160
–
M2S010
160
4
M2S025
160
4
M2S050
160
4
M2S080
–
–
M2S120
–
–
Note: User I/Os do not include the SERDES and JTAG pins.
FG484
484
1.0
23 × 23
I/Os
XCVRs
217
–
233
4
267
4
267
4
–
–
–
–
FG896
896
1.0
31 × 31
I/Os
XCVRs
–
–
–
–
–
–
377
8
–
–
–
–
FC1152
1,152
1.0
35 × 35
I/Os XCVRs
–
–
–
–
–
–
–
–
574
8
574
16
IV
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