M2S050TS-1FGG144YI Datasheet, PDF (91/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

ADVANCE INFORMATION (Subject to Change)
SmartFusion2 System-on-Chip FPGAs
Logic Module Specifications
4-input LUT (LUT-4)
The SmartFusion2 offers a fully permutable 4-input LUT. In this section, timing characteristics are
presented for a sample of the library.
PAD
PAD
PAD
PAD
A
B
C
D/S (where
applicable)
t_PD
ADN4 OR
Any
Y
Combinational
Logic
PAD
A, B, C, D, S
VDD
50%
50%
t_PD = Max(t_PD(RR), t_PD(RF), t_PD(FF), t_PD(FR))
where edges are applicable for the particular
combinatorial cell
GND
VDD
OUT
GND
VDD
OUT
50%
t_PD
(RR)
t_PD
(RF)
50%
t_PD
(FF)
50%
t_PD
(FR)
GND
50%
Figure 2-6 • LUT-4
Timing Characteristics
Table 2-77 • Combinatorial Cell Propagation Delays
Combinatorial Cell
Equation
INV
Y = !A
AND2
Y=A·B
NAND2
Y = !(A · B)
OR2
Y=A+B
NOR2
XOR2
XOR3
Y = !(A + B)
Y=A⊕B
Y=A⊕B⊕C
AND3
Y=A·B·C
AND4
Y=A·B·C·D
Parameter
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
–1
0.108
0.172
0.16
0.172
0.16
0.172
0.24
0.22
0.493
Std.
0.127
0.203
0.188
0.203
0.188
0.203
0.283
0.259
0.58
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Revision 0
2- 73