M2S050TS-1FGG144YI Datasheet, PDF (95/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

ADVANCE INFORMATION (Subject to Change)
SmartFusion2 System-on-Chip FPGAs
FPGA Fabric SRAM
Refer to the SmartFusion2 FPGA Fabric Architecture User’s Guide for more information.
FPGA Fabric Large SRAM (LSRAM)
Table 2-80 • RAM1K18
–1
Std.
Parameter
Description
Min. Max. Min. Max. Units
tcy
Clock Period
1.656 – 1.948 – ns
tclkmpwh Clock Minimum Pulse Width High
0.828 – 0.974 – ns
tclkmpwl Clock Minimum pulse Width Low
0.327 – 0.384 – ns
tplcy
Pipelined Clock Period
1.652 – 1.944 – ns
tplclkmpwh Pipelined Clock Minimum Pulse Width High
0.826 – 0.972 – ns
tplclkmpwl Pipelined Clock Minimum pulse Width Low
0.324 – 0.381 – ns
tclk2q
Read Access Time with Pipeline Register
– 0.337 – 0.396 ns
Read Access Time without Pipeline Register
–
TBD – TBD ns
Access Time with Feed-Through Write Timing
–
TBD – TBD ns
taddrsu Address Setup Time
0.207 – 0.244 – ns
taddrhd Address Hold Time
0.041 – 0.048 – ns
tdsu
Data Setup Time
0.33
– 0.389 – ns
tdhd
Data Hold Time
0.074 – 0.087 – ns
tblksu
Block Select Setup Time (With Pipe-Line Register Enabled) 0.188 – 0.221 – ns
tblkhd
Block Select Hold Time (With Pipe-Lined Register Enabled) 0.079 – 0.093 – ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined –
Registered is Disabled)
TBD – TBD ns
Block Select to Out Enable Time (when Pipe-Lined Registered –
is Disabled)
TBD – TBD ns
tblkmpw Block Select Minimum Pulse Width
TBD
– TBD – ns
trdesu
Read Enable Setup Time (A_WEN, B_WEN =0)
0.465 – 0.547 – ns
trdehd
Read Enable Hold Time (A_WEN, B_WEN =0)
0.053 – 0.063 – ns
trdplesu Pipelined Read Enable Setup Time (A_DOUT_EN, 0.703 – 0.827 – ns
B_DOUT_EN)
trdplehd
tr2q
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
Asynchronous Reset to Output Propagation Delay
–0.053 – –0.062 – ns
- 0.792 – 0.931 ns
trstrem Asynchronous Reset Removal Time
TBD
– TBD – ns
trstrec Asynchronous Reset Recovery Time
0.005 – 0.006 – ns
trstmpw Asynchronous Reset Minimum Pulse Width
0.323 – 0.38 – ns
tplrstrem Pipelined Register Asynchronous Reset Removal Time ^{TBD – TBD – ns}
tplrstrec Pipelined Register Asynchronous Reset Recovery Time ^{0.344 – 0.405 – ns}
tplrstmpw Pipelined Register Asynchronous Reset Minimum Pulse Width 0.307 – 0.361 – ns
tsrstsu
Synchronous Reset Setup Time
0.231 – 0.271 – ns
Revision 0
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