M2S050TS-1FGG144YI Datasheet, PDF (1/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

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SmartFusion2 System-on-Chip FPGAs
Microsemi’s SmartFusion^®2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM^® Cortex™-M3 processor,
and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most
reliable and highest security programmable logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate
count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded
memory options and math blocks for digital signal processing (DSP). The 166 MHz ARM Cortex-M3 processor is enhanced with an
embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals including
controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include
peripheral component interconnect express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) +
native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide
high speed memory interfaces.
SmartFusion2 Family
Reliability
• Single Event Upset (SEU) Immune
– Zero FIT FPGA Configuration Cells
• Single Error Correct Double Error Detect (SECDED)
Protection on the Following:
– Ethernet Buffers
– CAN Message Buffers
– Cortex-M3 Embedded Scratch Pad Memory
(eSRAMs)
– USB Buffers
– PCIe Buffer
– DDR Memory Controllers with Optional SECDED
Modes
• Buffers Implemented with SEU Resistant Latches on the
Following:
– DDR Bridges (MSS, MDDR, FDDR)
– Instruction Cache
– MMUART FIFOs
– SPI FIFOs
• NVM Integrity Check at Power-Up and On-Demand
• No External Configuration Memory Required—Instant-
On, Retains Configuration When Powered Off
Security
• Design Security Features (available on all devices)
– Intellectual Property (IP) Protection via Unique
Security Features and Use Models New to the PLD
Industry
– Encrypted User Key and Bitstream Loading,
Enabling Programming in Less-Trusted Locations
– Supply-Chain Assurance Device Certificate
– Enhanced Anti-Tamper Features
– Zeroization
• Data Security Features (available on premium devices)
– Non-Deterministic Random Bit Generator (NRBG)
– User Cryptographic Services (AES-256, SHA-256,
Elliptical Curve Cryptographic (ECC) Engine)
– User Physically Unclonable Function (PUF) Key
Enrollment and Regeneration
– CRI Pass-Through DPA Patent Portfolio License
– Hardware Firewalls Protecting Microcontroller
Subsystem (MSS) Memories
Low Power
• Low Static and Dynamic Power
– Flash*Freeze Mode for Fabric
• For the M2S050 Device:
– < 1 mW in Flash*Freeze Mode
– 10 mW in Standby Mode
• Based on 65 nm Nonvolatile Flash Process
High-Performance FPGA
• Efficient 4-Input LUTs with Carry Chains for High
Performance and Low Power
• Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large
SRAM) with 400 MHz Synchronous Performance (x18,
x9, x4, x2, x1)
• Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2
Read Ports and 1 Write Port (micro SRAM)
• High Performance DSP Signal Processing
– Up to 240 Fast Math Blocks with 18 x 18 Signed
Multiplication, 17 x 17 Unsigned Multiplication and
44-Bit Accumulator
October 2012
I
© 2012 Microsemi Corporation