M2S050TS-1FGG144YI Datasheet, PDF (23/156 Pages) Microsemi Corporation – SmartFusion2 System-on-Chip FPGAs

ADVANCE INFORMATION (Subject to Change)
SmartFusion2 System-on-Chip FPGAs
Calculating Power Dissipation
Quiescent Supply Current
Table 2-4 • Quiescent Supply Current Characteristics
Parameter
IDC1
IDC2
IDC3
Modes
Active mode
Standby mode
Flash*Freeze mode
M2S050T
VDD = 1.2 V
7.5
7.5
0.387
Units
mA
mA
mA
I/O Power
Table 2-5 • Summary of I/O Input Buffer Power (per pin)
Using Default Software Setting with Technology Selected
MSIO I/O Bank
Static
Power
Dynamic
Power
PDC8
PAC9
(mW) (µW/MHz)
MSIOD I/O Bank
Static
Power
Dynamic
Power
PDC8
(mW)
PAC9
(µW/MHz)
Single Ended I/O Standards
1.2 V LVCMOS (JESD8-11)
0.00
11.72
0.00
11.72
1.5 V LVCMOS (JESD8-11)
0.00
8.32
0.00
8.32
1.8 V LVCMOS
0.00
10.69
0.00
10.69
2.5 V LVCMOS
0.00
4.14
0.00
4.14
3.3 V LVTTL / 3.3 V LVCMOS
0.00
5.47
–
–
3.3 V PCI/PCIX
0.00
1.82
–
–
Memory Interface and Voltage Reference Standard
HSTL 1.5 V
2.21
5.57
2.21
5.57
HSTL 1.5 V – True differential
1.25
47.38
1.25
47.38
SSTL2/DDR
10.02
42.68
10.02
42.68
SSTL2/DDR – True differential
4.39
12.35
4.39
12.35
SSTL18/DDR2
3.88
3.81
3.88
3.81
SSTL18/DDR2 – True differential 1.97
56.80
1.97
56.80
SSTL15/DDR3
–
–
–
–
SSTL15/DDR3 – True differential
–
–
–
–
LPDDR
–
–
–
–
LPDDR – True differential
–
–
–
–
Differential Standards
LVDS
5.74
17.65
5.74
17.65
B-LVDS
5.65
8.76
5.65
8.76
M-LVDS
5.65
8.76
5.65
8.76
RSDS
5.74
0.93
5.74
0.93
Mini-LVDS
TBD
TBD
TBD
TBD
LVPECL
TBD
TBD
–
–
DDR I/O Bank
Static Dynamic
Power Power
PDC8 PAC9
(mW) (µW/MHz)
Notes
0.00
11.72
0.00
8.32
0.00
10.69
0.00
4.14
–
–
–
–
2.21
1.25
10.02
4.39
3.88
1.97
2.20
1.23
3.88
1.97
5.57
47.38
42.68
12.35
3.81
56.80
18.00
46.81
4.46
5.08
–
–
–
–
–
–
–
–
–
–
–
–
Revision 0
2-5