CCU3000 Datasheet, PDF (68/77 Pages) Micronas – Central Control Unit

CCU 3000,-IC, CCCUU30300-1I-I
CCU 3001, CCU 3001-I
Table 2–1: I²C and IM bus interface registers
Address
2D0H(w)
2D1H(w)
2D2H(w)
2D3H(w)
2D4H(w)
2D5H(w)
2D6H(r)
2D7H(r)
2D8H(w)
2D9H(w)
2DAH(w)
2DBH(w)
Function
generate I²C start condition,
transfer Data as I²C address,
and set ACK=1
same as above, ACK=0
output 8 I²C Data bits,
set ACK=1
same as above, set ACK=0
output 8 I²C Data bits,
set ACK=1,
generate I²C stop condition
same as above,
set ACK=0
receive FIFO
status flags:
bit 0
not used
bit 1
1= receive
FIFO empty
bit 2
1= contr-data-
FIFO half full
bit 3
1= Bus busy
bit 4
I²C data ACK
bit 5
I²C adr ACK
bit 6
“OR”ed ACK
bit 7
not used
generate IM-address field
generate 8 IM-data bits
generate 8 IM-data bits and
the IM-stop condition
terminal select & speed
For example, the software has to work off the following
sequence (ACK =1) to read a 16-bit word from an I²C de-
vice address 10H (on condition that the bus is not ac-
tive):
–write 21H to
2D0H
–write 0FFH to 2D2H
–write 0FFH to 2D4H
–read dev. address2D6H
–read 1. databyte 2D6H
–read 2. databyte 2D6H
check
receive
FIFO empty flag
(bit 1, 2D7H) be-
fore read
The value 21H in the first step results from the device ad-
dress in the 7 MSBs and the R/W-bit (read=1) in the LSB.
If the telegrams are longer, the software has to ensure
that neither the Control-Data-FIFO nor the Read-FIFO
can overflow.
To write data to this device:
–write 20H to
–write 1. databyte to
–write 2. databyte to
2D0H
2D2H
2D4H
The bus activity starts immediately after the first write to
the Control-Data-FIFO. In the I²C mode the transmis-
sion can be synchronized by an artificial extension of the
Low phase of the clock line. Transmission is not contin-
ued until the state of the clock line is High once again.
Thus a slave (software slaves!) can adjust the transmis-
sion rate to its own abilities.
The I ²C/IM bus interface is a pure Master system, Multi-
master busses are not realizable.
The ident, clock and data terminal pins have open-drain
outputs with weak pull-up transistors.
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