CCU3000 Datasheet, PDF (10/77 Pages) Micronas – Central Control Unit

CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
2.11. Interrupt Controller
The most important properties of this controller are:
– 8 sources
– 8 freely programmable priorities for every source
– maximum delay of 3 clock cycles
– vectorized interrupts, i.e., automatically the correct
routine is accessed
– also to be used for external CPU
– option: disable after interrupt (resettable by software)
Running service routines are only interrupted if inter-
rupts are enabled and a request of higher priority arrives.
All others are stored and executed when interrupts of
higher priority have been finished. Priority 0 means that
the corresponding interrupt is disabled. (Priorities 1-7
lead to interrupts). One property of the controller is that
the CPU is not modified, but vectorization takes place all
the same. Thus the use of this controller is also possible
for external CPUs (emulator!).
Solely the return from a service program differs slightly
in software from the methods normally used for the
65C02. The last command before the “RTI” must be a
write operation into the return register of the controller.
This tells the controller that the service routine has been
completed. Apart from this return register the controller
occupies further 5 bytes. One of these serves as a con-
trol byte, the others incorporate the priorities for 8
sources. The controller therefore needs 6 bytes of the
I/O-page. The control byte comprises:
bit 0 CLEAR_ALL_REQUESTS
bit 1 ALLOW_ONE_INTERRUPT
bit 2 DISABLE_INTERRUPTS
bit 3 DISABLE_AFTER_INT
bit 4 RESET_CONTROLLER
(low active)
(low active)
(low active)
(low active)
(low active)
All bits reset to 1 (inactive).
CLEAR_ALL_REQUESTS clears all interrupt flags at
the same time. ALLOW_ONE_INTERRUPT is used in
connection with the DISABLE_AFTER_INT (bit 3), to al-
low access to the next interrupt. DISABLE_INTERRUPT
does not allow any interrupts, the request flags are set
however. With the exception of bits 3 and 2 (DIS-
ABLE_INTERRUPTS, DISABLE_AFTER_INT) these
are all dynamic signals, that is, the write process itself
sends an appropriate signal. This has the same impulse
length as the 65C02. Each of the 4 priority registers con-
tains the priorities for 2 interrupt sources.
bit 7, 6, 5, 4
bit 3, 2, 1, 0
Priority for sources
8, 6, 4, 2
Priority for sources
7, 5, 3, 1
To connect an external CPU (emulator) with the control-
ler, only two ICs of the 74-family are needed.
Φ2
ADB
DB
CTRLQ
Fig. 2–9: Dynamic control signals interrupt
Bits 0, 1, 4
Φ2
ADB
DB
CTRLQ
Fig. 2–10: Static control signals interrupt
Bits 2, 3
10
MICRONAS INTERMETALL