CCU3000 Datasheet, PDF (13/77 Pages) Micronas – Central Control Unit

CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
write:
bit 0 1... Write 8 bit
bit 1 1... Write 16 bit
bit 2 1... Read 8 bit
bit 3 1... Read 16 bit
1 byte Data
rate (5 bits)
=
fosc
4. n
Only one of the bits 0 to 3 in the control register should
be set. If all bits are set to ‘0‘, a reset of the interface is
CPU
data bus
done, thus deleting telegrams still waiting for access to
the bus. The IM bus addresses for the slave registers
are:
Slave register
1
2
3
IM bus address
02 H
03 H
04 H
Slave
1
Slave
Interface
IM Bus addresses
2, 3 and 4
ID
Data
CLK
Slave
2
slave
register 1 (IM Bus
address 02H)
received data
(1 byte)
Slave
3
3
Contr. _Mode
Master Ready
INT
INT
4
transmission
completed
Data
Addr.
Master
Interface
Rate
Data rate
n
Fig. 2–13: IM bus interface
MICRONAS INTERMETALL
fosc
fosc
Data rate: f_IM = _{4 . n} ; n = _{4 . fIM}
13