CCU3000 Datasheet, PDF (38/77 Pages) Micronas – Central Control Unit

CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
4.6.10. Registers
0200H
Bit
7 to 3
2
1
0
System Clock Prescaler
Reset
Read
0
x
1
x
0
x
0
x
Write
Divisor value –1
0201H
Bit
7
6
5
4
3
2
1
0
Control Register
Reset
Read
copy
x
from
addr.
x
FFF9H
x
external bus: ‘1’ = bus on ports 0, 1, 2
disabled
R/W signal / Port4: ‘0’ = R/W, ‘1’ = P40
internal ROM: ‘1’ = internal ROM
enabled
internal RAM: ‘1’ = internal RAM enabled
internal CPU: ‘1’ = internal CPU enabled
Write
no function – set to ‘1’ (to keep
compatibility)
no function – set to ‘1’ (to keep
compatibility)
no function – set to ‘1’ (to keep
compatibility)
Bus disable: ‘1” = disable bus on ports
0, 1, 2
R/W signal / Port4: ‘0’ = R/W, ‘1’ = P40
ROM enable: ‘1’ = enable internal ROM
RAM enable: ‘1’ = enable internal RAM
CPU enable: ‘1’ = enable internal CPU
0202H
Bit
7
6
5
4
3
2
1
0
Watchdog Control and Status
Reset
Read
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1/0
‘0’: last RESET was generated by
watchdog
38
Write
Watchdog time value =
( ^fsystem
65536
*
Twd )
–1 = n
T_wd = (n+1) * 65536
(don’t use setting n<2!!)
f_system
with f_system = 4 MHz:
n = n_min = 2 ⇒ T_wdmin = 49.152 ms
n = n_max = 255 ⇒ T_wdmax = 4.17792 s
min. ∆n = 1 ⇒ min. ∆T _wd =16.384 ms
MICRONAS INTERMETALL