CCU3000 Datasheet, PDF (21/77 Pages) Micronas – Central Control Unit

CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
2.15. IR-Input
The IR-interface consists of two parallel edge detectors
which trigger the rising and falling edge. The respective
state of the rising edge triggered flip-flop can be read
from D0 (triggered positively), or D1 (triggered nega-
tively). Any read event via the CPU deletes both flip-
flops. D2 reflects the status of the IR pin, D3 to D7 are
set to 0.
If the CPU is switched off, the IR-Interface is no longer
available, as the IR pin is used as output for the interrupt
controller. For use as an emulator this function has to be
rebuilt externally. The I/O-address designed for the IR-
INPUT is treated as an external address when the CPU
is switched off, so that the software can remain un-
touched.
2.16. Mask Options
There are two mask options:
OSC option:
if this option is set, X₁ and X₂ can be
used as clock input and output or as
XTAL pins, (depending on control
word bit 5)
RES option:
if this option is set, the reset sources
Power on and Clock Supervision
are disabled with bit 0 of the test
register 2FFH. Default = enabled).
In the production version none of the options is set, in the
EMU version both are set.
CPU dis
‘1’
IR
‘0’
CLR
CLR
D0
RD IR
D1
Fig. 2–19: IR input
D2
from Interrupt
Controller
MICRONAS INTERMETALL
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