CCU3000 Datasheet, PDF (19/77 Pages) Micronas – Central Control Unit

CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
2.14. Watchdog
– not active after Reset
– activated when written, cannot be stopped via soft-
ware
– to retrigger, the watchdog period negated bit by bit
must be rewritten within the preset space of time (first
write event is also counted)
– triggers reset, the software can identify if Reset was
generated by watchdog
– 16 ms to 4 s time-out for 4 MHz system clock
This counter circuit offers hardware support for software
problems. It is disabled after reset and enabled with the
first write of the desired time value into its register. The
value to program is calculated by
n = T_WD * f_system / 65536 – 1
with n = watchdog counter value to be programmed for
T_WD = the desired watchdog time and
f_system = system frequency.
Remarks:
a) To prevent the generation of a ‘RESET’ by the watch-
dog before it could be retriggered by the software,
watchdog counter values less than 2 should not be pro-
grammed.
b) The system clock as input of the watchdog counter is
influenced by the system clock prescaler, determining
the CPU speed (register addr. 200 H).
Software can’t stop this counter but has to retrigger it by
writing the inverted value (one’s complement) of the pre-
ceding written pattern into its register, which makes un-
wanted retrigger loops of disturbed software unlikely.
These writes have to occur within the time frame (8 ms
to 2 s at 8 MHz system clock), defined with the first write.
If no write with the expected pattern occurs within the
programmed time period, the watchdog circuit resets the
CCU at the end of the time period. There will also be a
watchdog reset if another pattern is written instead of the
expected one. The software can detect if a reset was
generated by the watchdog: Bit 0 of the watchdog regis-
ter is ‘0’ if the last reset was generated by the watchdog.
This bit is reset only with an external reset, e.g. gener-
ated by power-on.
Examples:
To set a cycle time of 1 second with 8 MHz system clock
the value is 121. This value is calculated as follows:
system frequency: 8 MHz
watchdog cycle time:
65536 / 8 MHz = 8.192 ms,
counter value:
1 s / 8.192 ms = 122.07.
MICRONAS INTERMETALL
The nearest integer value is 122. Because a 0 loaded
into the counter divides by 1, already, the watchdog
counter has to be programmed with 122-1 = 121. With
the formula above
n = 121 = 1s * 8 MHz/65536 – 1
The software sequences in Assembler could look like
this:
Definitions:
;constants:
WATCHDOG_TIME
;CCU I/O–address:
watchdog_address
;variable:
watchdog_value
Example 1:
EQU
121
EQU
202H
EQU
30H ;(address
; of free RAM location)
During initialization the watchdog is filled with the de-
sired time-value:
LDA #WATCHDOG_TIME
STA watchdog_address
STA watchdog_value ;memorize
; watchdog pattern
In the main loop of the program the watchdog has to be
retriggered cyclically:
LDA watchdog_value
EOR #FFH
;invert bits
STA watchdog_address
STA watchdog_value ;memorize new
; watchdog pattern
Example 2:
If an interrupt function occurs cyclically, one value may
be programmed in the interrupt service routine, while the
other is written in the main loop. So both the continuity
of executing the interrupt service and the main loop are
checked:
During initialization the watchdog shadow variable is
filled with the desired time-value:
LDA #WATCHDOG_TIME
STA watchdog_value
;memorize
; watchdog pattern
Sequence in the interrupt function:
LDA watchdog_value
CMP #WATCHDOG_TIME
BEQ SKIP_IRQ_WD
;
STA watchdog_address
EOR #$FF
STA watchdog_value
SKIP_IRQ_WD
...
19