MSP34X0G Datasheet, PDF (54/96 Pages) Micronas – Multistandard Sound Processor Family

MSP 34x0G
4.5. Pin Circuits
Pin numbers refer to the PQFP80 package.
DVSUP
P
N
GND
Fig. 4–11: Output Pins 6, 8, 9, and 10
(I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL)
PRELIMINARY DATA SHEET
DVSUP
P
N
GND
Fig. 4–15: Input/Output Pins 4, 5, 77, and 78
(I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
N
GND
Fig. 4–12: Input/Output Pins 2 and 3
(I2C_CL, I2C_DA)
Fig. 4–13: Input Pins 7, 17, 21, 70, and 80
(I2S_DA_IN1, I2S_DA_IN2, RESETQ, TESTEN,
STANDBYQ)
DVSUP
23 kΩ
ADR_SEL
23 kΩ
GND
Fig. 4–14: Input Pin 79 (ADR_SEL)
P
3−30 pF
500 kΩ
N
2.5 V
3−30 pF
Fig. 4–16: Output/Input Pins 71, 72, and 74
(XTAL_IN, XTAL_OUT, AUD_CL_OUT)
ANA_IN1+
ANA_IN2+
A
D
ANA_IN−
VREFTOP
Fig. 4–17: Input Pins 58, 67, 68, and 69
(VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+)
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