MSP34X0G Datasheet, PDF (19/96 Pages) Micronas – Multistandard Sound Processor Family

PRELIMINARY DATA SHEET
3.2. Start-Up Sequence:
Power-Up and I²C Controlling
After POWER ON or RESET (see Fig. 4–24), the IC is
in an inactive state. All registers are in the reset posi-
tion (see tables 3–5 and 3–6), the analog outputs are
muted. The controller has to initialize all registers for
which a non-default setting is necessary.
3.3. MSP 34x0G Programming Interface
3.3.1. User Registers Overview
The MSP 34x0G is controlled by means of user regis-
ters. The complete list of all user registers is given in
the following tables. The registers are partitioned into
the Demodulator section (Subaddress 10_hex for writ-
ing, 11_hex for reading) and the Baseband Processing
sections (Subaddress 12_hex for writing, 13_hex for read-
ing).
Write and read registers are 16-bit wide, whereby the
MSB is denoted bit [15]. Transmissions via I²C bus
have to take place in 16-bit words (two byte transfers, with
the most significant byte transferred first). All write regis-
ters, except the demodulator write registers, are readable.
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be written.
For reasons of software compatibility to the
MSP 34x0D, an Manual/Compatibility Mode is avail-
able. More read and write registers together with a
detailed description of this mode can be found in the
“Appendix B: Manual/Compatibility Mode” on page 78.
An overview of all MSP 34x0G Write Registers is
shown in Table 3–5; all Read Registers are given in
Table 3–6.
MSP 34x0G
MICRONAS INTERMETALL
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