MSP34X0G Datasheet, PDF (15/96 Pages) Micronas – Multistandard Sound Processor Family

PRELIMINARY DATA SHEET
MSP 34x0G
3. Control Interface
3.1. I²C Bus Interface
3.1.1. Device and Subaddresses
The MSP 34x0G is controlled via the I²C bus slave
interface.
The IC is selected by transmitting one of the
MSP 34x0G device addresses. In order to allow up to
three MSP ICs to be connected to a single bus, an
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 34x0G responds to different device addresses. A
device address pair is defined as a write address (80,
84, or 88 hex) and a read address (81, 85, or 89 hex)
(see Table 3–1).
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condi-
tion, reading of the addressed data is completed by
sending the device read address (81, 85, or 89 hex)
and reading two bytes of data. Refer to section 3.1.3.
for the I²C bus protocol and to section “Programming
Tips” on page 39 for proposals of MSP 34x0G I²C tele-
grams. See Table 3–2 for a list of available subad-
dresses.
Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CON-
TROL register by the controller via I²C bus.
Due to the internal architecture of the MSP 34x0G, the
IC cannot react immediately to an I²C request. The
typical response time is about 0.3 ms. If the MSP can-
not accept another complete byte of data until it has
performed some other function (for example, servicing
an internal interrupt), it will hold the clock line I2C_CL
LOW to force the transmitter into a wait state. The
positions within a transmission where this may happen
are indicated by ’Wait’ in section 3.1.3. The maximum
wait period of the MSP during normal operation mode
is less than 1 ms.
Internal hardware error handling:
In case of any internal hardware error (e.g. interruption
of the power supply of the MSP), the MSP’s wait
period is extended to 1.8 ms. After this time period
elapses, the MSP releases data and clock lines.
Indication and solving of the error status:
1. MSP 34x0G-versions until B5: To indicate the
error status, all further acknowledge bits will be left
high. The MSP can then be reset by transmitting the
reset condition to CONTROL while ignoring the miss-
ing acknowledge bits.
2. MSP 34x0G-versions from B6 on: To indicate the
error status, the remaining acknowledge bits of the ac-
tual I²C-protocol will be left high. Additionally, bit[14] of
CONTROL is set to one. The MSP can then be reset
via the I²C bus by transmitting the reset condition to
CONTROL.
Indication of reset (only versions from B6 on):
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I²C bus is shown in
Fig. 4–25 on page 63.
MICRONAS INTERMETALL
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