MSP34X0G Datasheet, PDF (14/96 Pages) Micronas – Multistandard Sound Processor Family

MSP 34x0G
PRELIMINARY DATA SHEET
2.8. ADR Bus Interface
For the ASTRA Digital Radio System (ADR), the
MSP 3400G, MSP 3410G and MSP 3450G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x0G should be provided on a
feature connector:
– AUD_CL_OUT
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
– I2S_WS
– I2S_CL
– ADR_CL, ADR_WS, ADR_DA
For more details, please refer to the DRP 3510A data
sheet.
2.9. Digital Control I/O Pins and
Status Change Indication
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I²C-bus by means of the ACB register
(see page 37). This enables the controlling of external
hardware switches or other devices via I²C-bus.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 25).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 26).
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I²C bus interactions are reduced to a
minimum (see STATUS register on page 26 and
MODUS register on page 25).
2.10. Clock PLL Oscillator and Crystal Specifications
The MSP 34x0G derives all internal system clocks
from the 18.432-MHz oscillator. In NICAM or in I²S-
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I²S-Slave mode at the same time.
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note that for the
phase-locked modes (NICAM, I²S-Slave), crystals with
tighter tolerance are required.
Remark on using the crystal:
External capacitors at each crystal pin to ground are
required. They are necessary for tuning the open-loop
frequency of the internal PLL and for stabilizing the fre-
quency in closed-loop operation. The higher the
capacitors, the lower the resulting clock frequency.
The nominal free running frequency should match
18.432 MHz as closely as possible.
Clock measurements should be done at pin
AUD_CL_OUT. This pin must be activated for this pur-
pose (see Table 3–9 on page 25).
14
MICRONAS INTERMETALL