MSP34X0G Datasheet, PDF (2/96 Pages) Micronas – Multistandard Sound Processor Family

MSP 34x0G
PRELIMINARY DATA SHEET
Contents
Page
Section
5
1.
6
1.1.
6
1.2.
7
1.3.
8
2.
9
2.1.
9
2.2.
9
2.2.1.
9
2.2.2.
10
2.2.3.
10
2.2.4.
10
2.3.
12
2.4.
12
2.5.
12
2.5.1.
12
2.5.2.
12
2.5.3.
12
2.5.4.
13
2.6.
13
2.6.1.
13
2.6.2.
13
2.7.
14
2.8.
14
2.9.
14
2.10.
15
3.
15
3.1.
15
3.1.1.
16
3.1.2.
17
3.1.3.
18
3.1.4.
18
3.1.4.1.
18
3.1.4.2.
18
3.1.4.3.
18
3.1.4.4.
19
3.2.
19
3.3.
19
3.3.1.
22
3.3.2.
23
3.3.2.1.
23
3.3.2.2.
24
3.3.2.3.
25
3.3.2.4.
26
3.3.2.5.
27
3.3.2.6.
Title
Introduction
Features of the MSP 34x0G Family and Differences to MSPD
MSP 34x0G Version List
MSP 34x0G Versions and their Application Fields
Functional Description
Architecture of the MSP 34x0G Family
Sound IF Processing
Analog Sound IF Input
Demodulator: Standards and Features
Preprocessing of Demodulator Signals
Automatic Sound Select
Preprocessing for SCART and I²S Input Signals
Source Selection and Output Channel Matrix
Audio Baseband Processing
Automatic Volume Correction (AVC)
Loudspeaker and Headphone Outputs
Subwoofer Output
Quasi-Peak Detector
SCART Signal Routing
SCART DSP In and SCART Out Select
Stand-by Mode
I²S Bus Interface
ADR Bus Interface
Digital Control I/O Pins and Status Change Indication
Clock PLL Oscillator and Crystal Specifications
Control Interface
I²C Bus Interface
Device and Subaddresses
Description of CONTROL Register
Protocol Description
Proposals for General MSP 34x0G I²C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I²C Controlling
MSP 34x0G Programming Interface
User Registers Overview
Description of User Registers
STANDARD SELECT Register
Refresh of STANDARD SELECT Register
STANDARD RESULT Register
Write Registers on I²C Subaddress 10_hex
Read Registers on I²C Subaddress 11_hex
Write Registers on I²C Subaddress 12_hex
2
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