N25Q032A13ESE40F Datasheet, PDF (6/82 Pages) Micron Technology – SPI-compatible serial bus interface

32Mb, 3V, Multiple I/O Serial Flash Memory
Device Description
Device Description
The N25Q is a high-performance multiple input/output serial Flash memory device
manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionali-
ty, advanced write protection mechanisms, and a high-speed SPI-compatible bus inter-
face. Innovative, high-performance, dual and quad input/output instructions enable
double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Features
The memory is organized as 64 (64KB) main sectors that are further divided into 16 sub-
sectors each (1024 subsectors in total). The memory can be erased one 4KB subsector at
a time, 64KB sectors at a time, or as a whole.
The memory can be write protected by software through volatile and nonvolatile pro-
tection features, depending on the application needs. The protection granularity is of
64KB (sector granularity) for volatile protections
The device has 64 one-time programmable (OTP) bytes that can be read and program-
med with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be
permanently locked with a PROGRAM OTP command.
The device also has the ability to pause and resume PROGRAM and ERASE cycles by us-
ing dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
Operating Protocols
The memory can be operated with three different protocols:
• Extended SPI (standard SPI protocol upgraded with dual and quad operations)
• Dual I/O SPI
• Quad I/O SPI
The standard SPI protocol is extended and enhanced by dual and quad operations. In
addition, the dual SPI and quad SPI protocols improve the data access time and
throughput of a single I/O device by transmitting commands, addresses, and data
across two or four data lines.
XIP Mode
XIP mode requires only an address (no instruction) to output data, improving random
access time and eliminating the need to shadow code onto RAM for fast execution.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods
are available. For applications that must enter XIP mode immediately after power-up,
nonvolatile configuration register bit settings can enable XIP as the default mode.
PDF: 09005aef84566622
n25q_32mb_3v_65nm.pdf - Rev. G 9/12 EN
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