N25Q032A13ESE40F Datasheet, PDF (14/82 Pages) Micron Technology – SPI-compatible serial bus interface

Device Protection
32Mb, 3V, Multiple I/O Serial Flash Memory
Device Protection
Table 3: Data Protection using Device Protocols
Note 1 applies to the entire table
Protection by:
Power-on reset and internal timer
Command execution check
WRITE ENABLE operation
Description
Protects the device against inadvertent data changes while the power supply is out-
side the operating specification.
Ensures that the number of clock pulses is a multiple of one byte before executing a
PROGRAM or ERASE command, or any command that writes to the device registers.
Ensures that commands modifying device data must be preceded by a WRITE ENABLE
command, which sets the write enable latch bit in the status register.
Note: 1. Extended, dual, and quad SPI protocol functionality ensures that device data is protec-
ted from excessive noise.
Table 4: Memory Sector Protection Truth Table
Note 1 applies to the entire table
Sector Lock Register
Sector Lock
Down Bit
Sector Write Lock
Bit
Memory Sector Protection Status
0
0
Sector unprotected from PROGRAM and ERASE operations. Protection status re-
versible.
0
1
Sector protected from PROGRAM and ERASE operations. Protection status rever-
sible.
1
0
Sector unprotected from PROGRAM and ERASE operations. Protection status not
reversible except by power cycle or reset.
1
1
Sector protected from PROGRAM and ERASE operations. Protection status not
reversible except by power cycle or reset.
Note: 1. Sector lock register bits are written to when the WRITE TO LOCK REGISTER command is
executed. The command will not execute unless the sector lock down bit is cleared (see
the WRITE TO LOCK REGISTER command).
Table 5: Protected Area Sizes – Upper Area
Note 1 applies to the entire table
Status Register Content
Top/
Bottom
Bit
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
Memory Content
Protected Area
None
Upper 64th
Upper 32th
Upper 16th
Upper 8th
Upper 4th
Unprotected Area
All sectors
Sectors (0 to 62)
Sectors (0 to 61)
Sectors (0 to 59)
Sectors (0 to 55 )
Sectors (0 to 47)
PDF: 09005aef84566622
n25q_32mb_3v_65nm.pdf - Rev. G 9/12 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.