N25Q032A13ESE40F Datasheet, PDF (12/82 Pages) Micron Technology – SPI-compatible serial bus interface

32Mb, 3V, Multiple I/O Serial Flash Memory
Memory Organization
Memory Organization
Memory Configuration and Block Diagram
Each page of memory can be individually programmed. Bits are programmed from one
through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable.
Bits are erased from zero through one. The memory is configured as 4,194,304 bytes (8
bits each); 64 sectors (64KB each); 1024 subsectors (4KB each); and 16,384 pages (256
bytes each); and 64 OTP bytes are located outside the main memory array.
Figure 5: Block Diagram
HOLD#
W#/V_PP
S#
C
DQ0
DQ1
Control logic
High voltage
generator
I/O shift register
64 OTP bytes
Address register
and counter
256 byte
data buffer
3FFFFFh
Status
register
PDF: 09005aef84566622
n25q_32mb_3v_65nm.pdf - Rev. G 9/12 EN
00000h
000FFF
256 bytes (page size)
X decoder
12
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