N25Q032A13ESE40F Datasheet, PDF (59/82 Pages) Micron Technology – SPI-compatible serial bus interface

32Mb, 3V, Multiple I/O Serial Flash Memory
XIP Mode
Figure 30: XIP Mode Directly After Power-On
C
t_{VSI (<100µ)}
V_CC
NVCR check:
XIP enabled
S#
DQ0
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A[MIN]
Xb
LSB
D_OUT D_OUT D_OUT D_OUT D_OUT
DQ[3:1]
A[MAX]
D_OUT D_OUT D_OUT D_OUT D_OUT
MSB
Dummy cycles
Note: 1. Xb is the XIP confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit
XIP mode and return to standard read mode.
Confirmation Bit Settings Required to Activate or Terminate XIP
The XIP confirmation bit setting activates or terminates XIP after it has been enabled or
disabled. This bit is the value on DQ0 during the first dummy clock cycle in the FAST
READ operation. XIP requires at least one additional clock cycle to send the XIP confir-
mation bit to the memory on DQ0 during the first dummy clock cycle.
Table 28: XIP Confirmation Bit
Bit Value
0
1
Description
Activates XIP: While this bit is 0, XIP remains activated.
Terminates XIP: When this bit is set to 1, XIP is terminated and the device returns
to SPI.
Table 29: Effects of Running XIP in Different Protocols
Protocol
Extended I/O,
Dual I/O
Dual I/O
Effect
In a device with a dedicated part number where RST# is enabled, a LOW pulse on RST#
resets XIP and the device to the state it was in previous to the last power-up, as defined
by the nonvolatile configuration register.
Values of DQ1 during the first dummy clock cycle are "Don't Care."
Notes
PDF: 09005aef84566622
n25q_32mb_3v_65nm.pdf - Rev. G 9/12 EN
59
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.