N25Q032A13ESE40F Datasheet, PDF (34/82 Pages) Micron Technology – SPI-compatible serial bus interface

32Mb, 3V, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
Figure 12: WRITE LOCK REGISTER Command
Extended
C
0
7
8
C_x
LSB
A[MIN]
DQ[0]
Command
D_IN
D_IN
D_IN
D_IN
MSB
A[MAX]
MSB
D_IN
D_IN
D_IN
LSB
D_IN
D_IN
Dual
C
0
3
4
C_x
LSB
A[MIN]
LSB
DQ[1:0]
Command
D_IN
D_IN
D_IN
D_IN
D_IN
MSB
A[MAX]
MSB
Quad
C
0
1
2
C_x
DQ[3:0]
Command
MSB
LSB
A[MAX]
A[MIN]
D_IN
MSB
LSB
D_IN
D_IN
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, C_x = 1 + ((A[MAX] + 1)/4).
CLEAR FLAG STATUS REGISTER Command
To execute the CLEAR FLAG STATUS REGISTER command and reset the error bits
(erase, program, and protection), S# is driven LOW. For extended SPI protocol, the com-
mand code is input on DQ0. For dual SPI protocol, the command code is input on
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation
is terminated by driving S# HIGH at any time.
PDF: 09005aef84566622
n25q_32mb_3v_65nm.pdf - Rev. G 9/12 EN
34
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