MT41J128M16HA-15EDTR Datasheet, PDF (210/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
T0
CK#
CK
Command REF
CKE
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
Ta1
Ta2
Ta3
Ta4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_ANPD
PDE transition period
t_{RFC (MIN)}
PDX transition period
t_ANPD
Short CKE low transition period (R _TT change asynchronous or synchronous)
t_XPDLL
Note: 1. AL = 0, WL = 5, ^tANPD = 4.
Indicates break
in time scale
Transitioning
Don’t Care
Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
Command NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
t_ANPD
t_XPDLL
t_ANPD
Short CKE HIGH transition period (R_TT change asynchronous or synchonous)
Note: 1. AL = 0, WL = 5, ^tANPD = 4.
Indicates break
in time scale
Transitioning
Don’t Care