MT41J128M16HA-15EDTR Datasheet, PDF (194/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Dynamic ODT
Table 88: Mode Registers for R_TT(WR)
MR2 (R_TT(WR))
M10
M9
0
0
0
1
1
0
1
1
R_TT(WR) (RZQ)
R_TT(WR) (Ohm)
Dynamic ODT off: WRITE does not affect R_TT,nom
RZQ/4
60
RZQ/2
120
Reserved
Reserved
Table 89: Timing Diagrams for Dynamic ODT
Figure and Page
Figure 108 (page 195)
Figure 109 (page 195)
Figure 110 (page 196)
Figure 111 (page 197)
Figure 112 (page 197)
Title
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Dynamic ODT: Without WRITE Command
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
194
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