MT41J128M16HA-15EDTR Datasheet, PDF (158/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

Figure 67: Consecutive READ Bursts (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
Command¹
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_CCD
Address²
Bank,
Col n
Bank,
Col b
t_RPRE
t_RPST
DQS, DQS#
DQ3
RL = 5
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
RL = 5
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
Figure 68: Consecutive READ Bursts (BC4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
Command¹
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_CCD
Address²
Bank,
Col n
Bank,
Col b
t_RPRE
t_RPST
t_RPRE
t_RPST
DQS, DQS#
DQ3
RL = 5
DO
DO
DO
DO
n
n+1 n+2 n+3
RL = 5
DO
DO
DO
DO
b
b+1 b+2 b+3
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BC4, RL = 5 (CL = 5, AL = 0).