MT41J128M16HA-15EDTR Datasheet, PDF(132/211 Page) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

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MT41J128M16HA-15EDTR Datasheet, PDF (132/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

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2Gb: x4, x8, x16 DDR3 SDRAM

Initialization

Figure 48: Initialization Sequence

T (MAX) = 200ms

VDD

VDDQ

VTT

VREF

See power-up

conditions

in the

initialization

sequence text,

set up 1

Power-up

ramp

CK#

CK

tIOZ = 20ns

RESET#

CKE

Stable and

tVTD valid clock

T0

T1

tCK

tCKSRX tCL

tCL

T (MIN) = 10ns

tIS

ODT

Command

tIS

NOP

MRS

DM

MRS

Ta0

Tb0

Tc0

Td0

MRS

MRS

ZQCL

Valid

Valid

Valid

Address

Code

Code

Code

Code

Valid

A10

Code

Code

Code

Code

A10 = H

Valid

BA[2:0]

DQS

DQ

RTT

BA0 = L

BA1 = H

BA2 = L

BA0 = H

BA1 = H

BA2 = L

BA0 = H

BA1 = L

BA2 = L

BA0 = L

BA1 = L

BA2 = L

Valid

T = 200Î¼s (MIN)

T = 500Î¼s (MIN)

tXPR

tMRD

tMRD

tMRD

tMOD

tZQinit

All voltage

supplies valid

and stable

MR2

DRAM ready for

external commands

MR3

MR1 with

DLL enable

MR0 with

DLL reset

ZQ calibration

tDLLK

Indicates break

in time scale

Normal

operation

Donât Care

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

132

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