MT41J128M16HA-15EDTR Datasheet, PDF (135/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 0 (MR0)
ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Figure 51: Mode Register 0 (MR0) Definitions
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
M16 M15
00
01
10
11
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
0¹ 0 0 0¹ 0¹ PD WR DLL 0¹ CAS# latency BT CL
Mode Register
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
M12 Precharge PD
0 DLL off (slow exit)
1 DLL on (fast exit)
M8 DLL Reset
0 No
1 Yes
10
BL
Mode register 0 (MR0)
M1 M0
00
01
10
11
Burst Length
Fixed BL8
4 or 8 (on-the-fly via A12)
Fixed BC4 (chop)
Reserved
M11 M10 M9 Write Recovery
000
16
001
5
010
6
011
7
100
8
101
10
110
12
111
14
M6 M5 M4 M2 CAS Latency
0 0 0 0 Reserved
0010
5
0100
6
0110
7
1000
8
1010
9
1100
10
1110
11
0001
12
0011
13
0101
14
M3 READ Burst Type
0 Sequential (nibble)
1
Interleaved
Note: 1. MR0[17, 14, 13, 7] are reserved for future use and must be programmed to 0.
Burst Type
Accesses within a given burst may be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR0[3] (see Figure 51 (page 135)). The order-
ing of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are re-
stricted to nibble (BC4) or word (BL8) boundaries.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
135
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