MT41J128M16HA-15EDTR Datasheet, PDF (172/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

Figure 88: WRITE to READ (BC4 Mode Register Setting)
CK#
CK
Command¹
Address³
DQS, DQS#
DQ⁴
T0
WRITE
Valid
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
t_WTR2
t_WPRE
t_WPST
Valid
WL = 5
DI
DI
DI
DI
n
n+1 n+2 n+3
Indicates break
in time scale
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. ^tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T7.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at
Ta0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).