MT41J128M16HA-15EDTR Datasheet, PDF (206/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
Description
Power-down entry transition period
(power-down entry)
Power-down exit transition period
(power-down exit)
ODT to R_TT turn-on delay
(ODTLon = WL - 2)
ODT to R_TT turn-off delay
(ODTLoff = WL - 2)
t_ANPD
Min
Max
Greater of: ^tANPD or ^tRFC - refresh to CKE LOW
t_{ANPD +} t_XPDLL
Lesser of: ^tAONPD (MIN) (2ns) or
ODTLon × ^tCK + ^tAON (MIN)
Greater of: ^tAONPD (MAX) (8.5ns) or
ODTLon × ^tCK + ^tAON (MAX)
Lesser of: ^tAOFPD (MIN) (2ns) or
ODTLoff × ^tCK + ^tAOF (MIN)
Greater of: ^tAOFPD (MAX) (8.5ns) or
ODTLoff × ^tCK + ^tAOF (MAX)
WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK#
CK
CKE
Command NOP
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_ANPD
t_{RFC (MIN)}
PDE transition period
ODT A
synchronous
DRAM R_TT A
synchronous
ODT B
asynchronous
or synchronous
DRAM R_TT B
asynchronous
or synchronous
ODT C
asynchronous
DRAM R_TT C
asynchronous
R_TT,nom
ODTLoff
R_TT,nom
t_{AOF (MIN)}
t_{AOF (MAX)}
R_TT,nom
ODTLoff + ^tAOFPD (MIN)
t_{AOFPD (MAX)}
t_{AOFPD (MIN)}
ODTLoff + ^tAOFPD (MAX)
t_{AOFPD (MIN)}
t_{AOFPD (MAX)}
Indicates break
in time scale
Transitioning
Don’t Care
Note: 1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.