PIC16LF819-I Datasheet, PDF (94/176 Pages) Microchip Technology – Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
12.3 MCLR
PIC16F818/819 device has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR and excessive current beyond
the device specification during the ESD event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an
RC network, as shown in Figure 12-2, is suggested.
The RA5/MCLR/VPP pin can be configured for MCLR
(default) or as an I/O pin (RA5). This is configured
through the MCLRE bit in the Configuration Word
register.
FIGURE 12-2:
VDD
RECOMMENDED MCLR
CIRCUIT
PIC16F818/819
R1
1 kΩ (or greater)
C1
0.1 µF
(optional, not critical)
MCLR
12.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to VDD as
described in Section 12.3 “MCLR”. A maximum rise
time for VDD is specified. See Section 15.0 “Electrical
Characteristics” for details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating conditions are
met. For more information, see Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
DS39598E-page 92
12.5 Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC16F818/819 is
a counter that uses the INTRC oscillator as the clock
input. This yields a count of 72 ms. While the PWRT is
counting, the device is held in Reset.
The power-up time delay depends on the INTRC and
will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
12.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
12.7 Brown-out Reset (BOR)
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter #D005, about 4V) for longer than TBOR
(parameter #35, about 100 µs), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer (if enabled) will keep the device in
Reset for TPWRT (parameter #33, about 72 ms). If VDD
should fall below VBOR during TPWRT, the Brown-out
Reset process will restart when VDD rises above VBOR
with the Power-up Timer Reset. Unlike previous PIC16
devices, the PWRT is no longer automatically enabled
when the Brown-out Reset circuit is enabled. The
PWRTEN and BOREN configuration bits are
independent of each other.
12.8 Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR occurs.
Then, OST starts counting 1024 oscillator cycles when
PWRT ends (LP, XT, HS). When the OST ends, the
device comes out of Reset.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16F818/819 device operating in
parallel.
Table 12-3 shows the Reset conditions for the Status,
PCON and PC registers, while Table 12-4 shows the
Reset conditions for all the registers.
 2004 Microchip Technology Inc.