PIC16LF819-I Datasheet, PDF (30/176 Pages) Microchip Technology – Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
3.5 Reading Flash Program Memory
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1<7>) and then set control bit, RD
(EECON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle to read the data. This causes the
second instruction immediately following the
“BSF EECON1, RD” instruction to be ignored. The data
is available in the very next cycle in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDATH registers will hold this value until another read
or until it is written to by the user (during a write
operation).
EXAMPLE 3-3: FLASH PROGRAM READ
BANKSEL EEADRH
; Select Bank of EEADRH
MOVF ADDRH, W
;
MOVWF EEADRH
; MS Byte of Program
; Address to read
MOVF ADDRL, W
;
MOVWF EEADR
; LS Byte of Program
; Address to read
BANKSEL EECON1
; Select Bank of EECON1
BSF
EECON1, EEPGD ; Point to PROGRAM
; memory
BSF
EECON1, RD ; EE Read
;
NOP
; Any instructions
; here are ignored as
NOP
; program memory is
; read in second cycle
; after BSF EECON1,RD
BANKSEL EEDATA
; Select Bank of EEDATA
MOVF EEDATA, W ; DATAL = EEDATA
MOVWF DATAL
;
MOVF EEDATH, W ; DATAH = EEDATH
MOVWF DATAH
;
3.6 Erasing Flash Program Memory
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the Flash array is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 32 words of program memory
is erased. The Most Significant 11 bits of the
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
After the “BSF EECON1, WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not Sleep mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
3.6.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load EEADRH:EEADR with address of row
being erased.
2. Set EEPGD bit to point to program memory; set
WREN bit to enable writes and set FREE bit to
enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase.
DS39598E-page 28
 2004 Microchip Technology Inc.