PIC16LF819-I Datasheet, PDF (15/176 Pages) Microchip Technology – Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Detailson
POR, BOR page:
Bank 0
00h⁽¹⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
01h
TMR0
Timer0 Module Register
xxxx xxxx 53, 17
02h⁽¹⁾ PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 23
03h⁽¹⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 16
04h⁽¹⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx 23
05h
PORTA
PORTA Data Latch when written; PORTA pins when read
xxx0 0000 39
06h
PORTB
PORTB Data Latch when written; PORTB pins when read
xxxx xxxx 43
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
0Ah^(1,2)
0Bh⁽¹⁾
—
PCLATH
INTCON
Unimplemented
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 23
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 18
0Ch
PIR1
—
ADIF
—
—
SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 20
0Dh
PIR2
—
—
—
EEIF
—
—
—
—
---0 ----
21
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 57
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 57
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57
11h
TMR2
Timer2 Module Register
0000 0000 63
12h
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 64
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 71, 76
14h
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
xxxx xxxx 66, 67, 68
16h
CCPR1H
Capture/Compare/PWM Register (MSB)
xxxx xxxx 66, 67, 68
17h
CCP1CON
—
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 65
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx 81
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0 GO/DONE
—
ADON 0000 00-0 81
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
 2004 Microchip Technology Inc.
DS39598E-page 13