PIC16LF819-I Datasheet, PDF (16/176 Pages) Microchip Technology – Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Detailson
POR, BOR page:
Bank 1
80h⁽¹⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
81h
82h⁽¹⁾
83h⁽¹⁾
84h⁽¹⁾
85h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PCL
Program Counter’s (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
FSR
TRISA
Indirect Data Memory Address Pointer
TRISA7 TRISA6 TRISA5⁽³⁾ PORTA Data Direction Register (TRISA<4:0>
PS0 1111 1111 17, 54
0000 0000
23
C
0001 1xxx
16
xxxx xxxx
23
1111 1111
39
86h
TRISB
PORTB Data Direction Register
1111 1111
43
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
8Ah^(1,2)
8Bh⁽¹⁾
—
PCLATH
INTCON
Unimplemented
—
—
GIE
PEIE
—
Write Buffer for the upper 5 bits of the PC
TMR0IE
INTE
RBIE
TMR0IF
INTF
—
—
---0 0000
23
RBIF 0000 000x
18
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000
19
8Dh
PIE2
—
—
—
EEIE
—
—
—
—
---0 ----
21
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq
22
8Fh
90h⁽¹⁾
OSCCON
OSCTUNE
—
IRCF2
IRCF1
IRCF0
—
—
—
TUN5
TUN4
TUN3
IOFS
TUN2
—
TUN1
—
-000 -0--
38
TUN0 --00 0000
36
91h
—
Unimplemented
—
—
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I²C™ mode) Address Register
1111 1111
0000 0000
68
71, 76
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
72
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
81
9Fh
ADCON1
ADFM ADCS2
—
—
PCFG3 PCFG2 PCFG1
PCFG0 00-- 0000
82
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
DS39598E-page 14
 2004 Microchip Technology Inc.